Integrated circuits including resistivity changing memory cells are known. Resistivity changing memory cells may, for example, be magneto-resistive memory cells. Magneto-resistive memory cells involve spin electronics which combines semiconductor technology and magnetics. The spin of an electron, rather than the charge, is used to indicate the presence of a “1” or “0”. One such spin electronic device is a magnetic random-access memory (MRAM) which includes conductive lines positioned perpendicular to one another in different metal layers, the conductive lines sandwiching a magnetic stack. The place where the conductive lines intersect is called a cross-point. A current flowing through one of the conductive lines generates a magnetic field around the conductive line and orients the magnetic polarity into a certain direction along the wire or conductive line. A current flowing through the other conductive line induces the magnetic field and can also partially turn the magnetic polarity. Digital information, represented as a “0” or “1”, is stored in the alignment of magnetic moments. The resistance of the magnetic component depends on the moment's alignment. The stored state is read from the element by detecting the component's resistive state. A memory cell may be constructed by placing the conductive lines and cross-points in a matrix structure or array having rows and columns.
As an example of an integrated circuit having magneto-resistive memory cells, FIG. 1 illustrates a perspective view of a part of a MRAM chip 110 having bit lines 112 located orthogonal to word lines 114 in adjacent metallization layers. Magnetic stacks 116 are positioned between the bit lines 112 and word lines 114 adjacent and electrically coupled to bit lines 112 and word lines 114. Magnetic stacks 116 preferably include multiple layers, including a soft layer 118, a tunnel layer 120, and a hard layer 122, for example. Soft layer 118 and hard layer 122 preferably include a plurality of magnetic metal layers, for example, eight to twelve layers of materials such as PtMn, CoFe, Ru, and NiFe, as examples. A logic state is storable in the soft layer 118 of the magnetic stacks 116 located at the junction of the bit lines 112 and word lines 114 by running a current in the appropriate direction within the bit lines 112 and word lines 114 which changes the resistance of the magnetic stacks 116.
In order to read the logic state stored in the soft layer 118 of a selected magnetic stack 116, a schematic such as the one shown in FIG. 2, including a sense amplifier (SA) 230, is used. A reference voltage UR is applied to one end of the selected magnetic stack 116. The other end of the selected magnetic stack 116 is coupled to a measurement resistor Rm1. The other end of the measurement resistor Rm1 is coupled to ground. The current running through the selected magnetic stack 116 is equal to current Icell. A reference circuit 232 supplies a reference current Iref that is run into measurement resistor Rm2. The other end of the measurement resistor Rm2 is coupled to ground, as shown.
It is desirable to improve the reliability of semiconductor devices as described above during operation.